Field of the Invention
This invention relates to processor systems, and more particularly to an improved method and means for accommodating variable amounts of memory resident on pluggable devices potentially exceeding the available memory address space of the system.
Description of the Prior Art
During the power on sequence of various personal computers and intelligent work stations, a range of code residing in Read Only Storage (ROS) is automatically executed. This code initializes the system such that the hardware is tested, put into a known state, and system parameters are defined. As part of this sequence, a number of hardward adapters must be initialized.
Typically, each adapter has its own ROS associated with it and the base ROS (on the system board) implements a well defined algorithm to identify these adapter ROS modules and execute them. Each adapter then requires a certain range of address space with the systems memory map. As more and more adapters are integrated into the system, more and more system memory address space is consumed. Since memory address space is a finite resource, the administration of address space become a difficult problem.
Additionally, many adapters' ROS modules must provide code to service hardware interrupts associated with the device. This does two things:
1. Places a greater demand on limited address space
2. Requires a solution to the address space problem to allow continued support of an interrupt handler operation.
Techniques are known in the prior art for maximizing use of system address space by eliminating gaps between volumes requisitioned by devices. In a system described in U.S. Pat. No. 4,025,903, memory is provided as pluggable modules with self-adjusting addressing by communication amongst themselves. The size of the address space required by each individual module is permanently stored in the module and is used to calculate, internally of each module, the memory addresses of the module (i.e., the device) based on an address communicated by the next lower module. While such systems eliminate waste in adress space assignment, the address space required is still the aggregate of the individual device requirements and may exceed the address space available.
In the prior art, limitation of address space has been relieved by memory address expansion schemes. For example, in some systems, data is placed in one address volume and commands in another. In other systems, high order bits of each address are used to point to registers in a matrix which supply a larger number of bits which replace those high order bits so as to create an address space of increased size. Such prior art schemes, while useful in individual employments, carry with them system architecture requirements which cannot be satisfied by simple modification of systems designed for a single, fixed size address scheme.
It is also known to provide add-on feature units having a numerical rank in which they are serviced. For example, features added to a system may share a common attention line, and when a general poll is passed to the features, the identity of the lowest numbered feature requiring service is returned in terms of its number.